Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of large a system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow include hardware description language (HDL) creation for a system and synthesis, placement, and routing of the system on the target device.
Soft processors are among the components that can be implemented on target devices. Soft processors are configurable processor cores that can be implemented on a programmable chip using resources available on the chip. Designers often specify a design for a soft processor to be implemented on the target device prior to developing and finalizing code to be executed on the soft processor. As a result, the soft processor may include hardware that is unused by the program. The unused hardware may take up valuable space on the target device. In addition, soft processors designed prior to finalizing the code to be executed may utilize memory resources on the target device in an inefficient manner.